Swarm Robotics Programming Language

Swarm robotics originates from the intersection of swarm intelligence and collective robotics. Swarm robotics systems are envisioned for large-scale application scenarios that require reliable, scalable, and autonomous behaviours. Among the many hurdles facing the deployment of swarm robotics systems, one of the most important is the lack of dedicated tools, especially regarding software. In particular, one problem that has received little attention in the literature is programmability. The current practice typically follows a bottom-up approach, whereby the focus is on individual behaviours and low-level interactions. This approach burdens developers with unnecessary detail, slowing both the development process and the advancement of the research field as a whole. The main goal of this project is to investigate approaches to realize a programming language specifically designed for swarm robotics. The official site for the language is here, code and tools can be downloaded from Github.

Select Publications

  • Carlo Pinciroli and Giovanni Beltrame. Buzz: a programming language for robot swarms. IEEE Software, 33(4):97–100, July/August 2016.
  • Carlo Pinciroli and Giovanni Beltrame. Buzz: an extensible programming language for heterogeneous swarm robotics. In Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS 2016), October 2016.
  • Carlo Pinciroli, Adam Lee-Brown, and Giovanni Beltrame. A tuple space for data sharing in robot swarms. In 9th EAI International Conference on Bio-inspired Information and Communications Technologies (BICT 2015). ACM Digital Library, 2015.

Students & Research Staff



Media coverage


An Internet-of-Things Platform for Humanitarian Aid

The aim of this project is to investigate novel approaches to create a self-organizing Internet-of-Things (IoT) platform to help first responders deal with the lack of communication and failing infrastructure in disaster areas. This is a strategic area for Canada, as we are currently on the verge of a new technology revolution—embedded devices and autonomous systems are becoming more and more present in our everyday lives. Communication, automation, and HCI are an enabling technology for many kinds of safety-critical applications, with our target of first response being one of the major drivers. Other examples of applications are industrial and agricultural monitoring, autonomous cars, and medical applications.

Our long-term objective is to construct a principled approach to the development of a self-organizing platform that mixes heterogeneous mobile systems, the cloud, and provides an intuitive interface for users and decision makers.

Students & Research Staff



Adaptive Computing Systems for Aerospace

Today’s computer systems are growing more and more complex at a pace that requires the development of novel and more effective methodologies to automate their design. Space, in particular, represents a challenging environment: without an atmosphere to protect from ionizing or particle radiation, current CMOS-based electronics are subject to transients faults, generalized performance reduction, accelerated wear, and, ultimately, unrecoverable system failure. Traditional approaches adopted to guarantee reliability and extended lifetime are based on redundancy which is fixed at design-time. However, these solutions are expensive in terms of resources and require a careful trade-off, because they increase complexity and area of the system, exposing it to a higher risk of overheating and radiation effects. Moreover, systems that are critical, time-constrained and where access is limited must be able to cope with situations where they cannot rely on human intervention. Therefore, there is an emerging interest in computer systems with adaptive capabilities that would be especially suited for novel high-performance embedded devices for aerospace.

Our aim is improving efficiency, fault-tolerance, and computational capabilities of aerospace computer systems. In our vision, this research will allow the creation of a new generation of computing systems that autonomously perform their tasks for longer periods of time, fostering simpler and cheaper space exploration.

Select Publications

  • Panerati J. and Beltrame G. (2014) Fault-tolerant Soft Real-time Computing Systems based on Dynamic Bayesian Reasoning, Proc. of International Astronautics Congress, Toronto, Canada

  • Panerati J., Abdi S., and Beltrame G. (2014) Balancing System Availability and Lifetime with Dynamic Hidden Markov Models, NASA/ESA Conference on Adaptive Hardware and Systems, Leicester, UK

  • Panerati J. and Beltrame G. (2014) A Comparative Evaluation of Multi-Objective Ex- ploration Algorithms for High-Level Design, ACM Transactions on Design Automation of Electronic Systems.

  • Panerati J., Sironi F., Carminati M., Maggio M., Beltrame G., Gmytrasiewicz P. J., Sciuto D., and Santambrogio M. D. (2013) On Self-Adaptive Resource Allocation through Reinforcement Learning, NASA/ESA Conference on Adaptive Hardware and Systems, Turin, Italy




Probabilistic Real Time Systems

Computing systems that are subject to strict operational deadlines from event (e.g. alarms, commands, etc.) to response are called real-time systems. These are employed in many applications where the response time of a control system can have a critical impact on the safety of people or infrastructure (e.g. airplanes, automobiles, or satellites). With critical applications become more and more complex, the performance of real-time systems has to increase to guarantee appropriate safety standards. The main obstacle to high-performance real-time systems is the unpredictable timing behaviour of modern computer architectures.

Currently, software designed for real-time systems needs to be guaranteed to be executed within the required time frame. Depending on the complexity of the underlying hardware architecture, this level of certainty might be difficult or impossible to reach. Within this context, this project will introduce a probabilistic approach: by enabling true randomized behaviour in processors and memory architectures, one can define probabilistic metrics for the timing behaviour of a system. This would bring real-time software engineering in line with other engineering domains, that perform risk analysis using component failure probabilities. In this project we will define novel architectures and design methodologies for truly probabilistic real-time systems, focusing on aerospace applications. Successful implementation of such systems will have tremendous impact on the way critical systems are designed, and the potential benefits in terms of cost of integration, verification, and certification of real-time software are enormous.

Select Publications

  • C. Chen, J. Panerati, and G. Beltrame. Effects of online fault detection mechanisms on probabilistic timing analysis. In 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS). Sept. 2016.
  • C. Chen, L. Santinelli, J. Hugues, and G. Beltrame. Static probabilistic timing analysis in presence of faults. In 11th IEEE International Symposium on Industrial Embedded Systems (SIES). May 2016.
  • H. Anwar and G. Beltrame. A probabilistically analysable cache implementation on fpga. In IEEE International NEW Circuits And Systems (NEWCAS). Grenoble, France, June 2015.




Hardware-aware Real-Time Code Generation

When developing simulation software, the development team has to rely on the competence of subject matter experts (SMEs) in different areas and with expertise from a multitude of domains, such as mechanics, power electronics, avionics, and more. In general, expecting SMEs to translate their domain knowledge into an imperative programming language is quite unrealistic, leading to the use of domain-specific languages (DSLs). On the other hand, by trading performance for usability to cope with software complexity, it had become increasingly difficult to extract the maximum performance from the hardware without a considerable knowledge of the hardware and expertise in parallel programming. The purpose of this project is to define a methodology for hiding software complexity from SMEs by automating the software generation, mapping and optimization according to inputs from SMEs and hardware and software experts, who describe the execution platform in sufficient detail. This methodology will be applied in particular to the aerospace industry’s Full Mission Simulators (FMSs), which are applications that are developed and maintained by multiple SMEs.

The overall result of this approach will be cost-effective and interoperable software products that will give a competitive advantage to the aerospace industry of Canada and Quebec.

Select Publications

  • Rabeh Ayari, Imane Hafnaoui, Alexandra Aguiar, Patricia Gilbert, Michel Galibois, Jean-Pierre Rousseau, Giovanni Beltrame, and Gabriela Nicolescu. Multi-objective mapping of full-mission simulators on heterogeneous distributed multi-processor systems. The Journal of Defense Modeling and Simulation: Applications, Methodology, Technology, 2016.
  • Rabeh Ayari, Imane Hafnaoui, Giovanni Beltrame, and Gabriela Nicolescu. Schedulability-guided crossover operator for real-time scheduling on heterogeneous multi-core systems. In Proceedings - IEEE International Symposium on Rapid System Prototyping, RSP. Pittsburgh, PA, United States of America, 2016.
  • Imane Hafnaoui, Rabeh Ayari, Gabriela Nicolescu, and Giovanni Beltrame. Simulation-based model generator for software performance estimation. In Proceedings of the Conference on Summer Computer Simulation. Society for Computer Simulation International, 2016




ICTherm: Thermal modelling

ICTherm is a library for the thermal modeling of electronic devices. It is multi-scale and it allows to easily model and simulate the thermal behavior of modern integrated circuits, such as 3D-ICs with TSVs, microfluidic systems, and full devices. ICTherm uses novel algorithms that enable extremely fast yet accurate simulations. The library is written in C and runs on GNU/Linux systems.

Select Publications and Patents

  • A Fourmigue, G Beltrame, G Nicolescu, Efficient Transient Thermal Simulation of 3D ICs with Liquid-Cooling and Through Silicon Vias, In Proc. of Design, Automation and Test in Europe (DATE), pp. 1385-1390, Dresden, Germany, Mar. 2014

  • A. Fourmigue, G. Beltrame, G. Nicolescu and E.M. Aboulhamid, A linear-time approach for the transient thermal simulation of liquid-cooled 3D ICs. In Proc. of CODES+ISSS, pp. 197-205, Taipei, Taiwan, Oct. 2011

  • A. Fourmigue, G. Beltrame, G. Nicolescu, E.M. Aboulhamid and I. O’Connor, Multi-granularity thermal evaluation of 3D MPSoC architectures. In Proc. of Design, Automation and Test in Europe (DATE), pp. 1-4, Grenoble, France, Mar. 2011


ICTherm - demo version of our thermal simulator



Radiation-tolerant FPGA architectures

Outside the protective cocoon of Earth’s atmosphere, extreme temperature changes, vacuum and a high radiation, make for a particularly harsh environment for electronic systems. The design of space-grade hardware (usually referred to as “hardened components”) requires large investments in infrastructure, and its development usually relies on government or military projects. However, with the recent opening of the space sector to private enterprises, the market faces a growing interest for the use of low-cost, off-the-shelf components (COTS). These components have to be properly screened and the design of computer systems has to take into account and work around their vulnerabilities. Current research focuses on using COTS in fault-tolerant configurations to obtain reliable systems that can be successfully used in space missions. The benefits of this research are not limited to the space segment: current technology trends— smaller feature sizes, lower voltage levels, higher operating frequencies —are projected to cause an increase in the failure rate of integrated circuits. Similar fault-tolerance strategies used in space applications can be used to mitigate these effects.

Field Programmable Gate Arrays (FPGAs) are programmable hardware devices, and are generally used for hardware prototyping. FPGAs typically have a higher cost per device manufactured, and lower performance when compared to custom devices produced in large volumes. Nevertheless, their constant evolution has made them a very attractive proposition for the small-volume aerospace market: they can be programmed with complex architectures with sufficient performance, for a fraction of the cost of producing a custom integrated circuit. FPGAs come in different flavours, and the most common, are the FLASH and SRAM kinds. These, in their non-military versions, are particularly sensitive to particle radiation (neturons, protons and other ions), the effects of which, called Single Event Effects (SEEs), can disrupt their normal behaviour. Our objective is to define low-cost systems, based on FPGAs, that are tolerant to SEEs, without excessively reducing their performance or functionality.


MORFIN - an orbital-realistic fault-injector




Auditory Orientation Aid for Astronauts

So. Let’s imagine that after many years of dreaming, you’re going into space! Unfortunately, when you get into orbit, you’re miserable! Like most astronauts, you experience malaise, disorientation, dizziness, nausea, and even vomiting. For a long-duration mission, space adaptation sickness is a fairly minor inconvenience, but if you have only a few days in space to work or play, of course it’s more of a problem. We propose a simple solution: provide an additional reference in the form of an auditory signal, perceived as coming from Earth. We hope to make commercial spaceflight more enjoyable.

This project’s purpose is to create a device that provides orientation reference information in microgravity environments. The device must be comfortable and must not interfere with crew communication or add to already high noise levels found on spacecraft.

TRAP: Fast instruction set simulation

TRAP (TRansaction level Automatic Processor generator) is a tool for the automatic generation of processor simulators starting from high level descriptions. This means that the developer only need to provide basic structural information (i.e. the number of registers, the endianess etc.) and the behavior of each instruction of the processor ISA; this data is then used for the generation of C++ code emulating the processor behavior. Such an approach consistently eases the developer’s work (with respect to manual coding of the simulator) both because it requires only the specification of the necessary details and because it forces a separation of the processor behavior from its structure. The tool is written in Python and it produces SystemC based simulators. With respect to standard ADL, having the input directly from Python eliminates the need for having an ad-hoc front-end thus consistently reducing the development effort.


ReSP: Virtual platform technology

ReSP is an MPSoC simulation platform working at a high abstraction level; components used by ReSP are based on SystemC and TLM hardware and communication description libraries. ReSP provides a non-intrusive framework to manipulate SystemC and TLM objects. The simulation platform is built using Python programming language; its reflective capabilities augment the platform with the possibility of observing the internal structure of the SystemC component models. This feature enables run-time composition and dynamic management of the architecture under analysis. The full potentialities offered by the integration among Python and SystemC are exploited, during simulation, to query, examine and, possibly, modify the internal status of the hardware models. These capabilities simplify the debugging process for both the modeled hardware architecture and the software running on it.

In order to add reflective capabilities to C++, wrappers around SystemC components must be created; they allow interoperability between C++ and Python languages. These wrappers are automatically created using Py++ tool.


InFault: Radiation-tolerance Verification

A novel approach to verify Single-Event-Upset (SEU) protection based on smart behavioral simulation. Our analysis does not require a testbench and can perform full, exhaustive coverage within less than an hour for typical designs.


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