Chao Chen




In 2008, I received B.Eng. degree with First Class Honours in EEE from University of Strathclyde (Glasgow, UK). I also received B.Sc. degree in EEE from North China Electric Power University (Beijing, China). In 2013, I was awarded the M.Sc. degree in Communications Engineering at RWTH Aachen University (Aachen, Germany). I am currently working as a PhD student in Computer Engineering at École Polytechnique de Montréal (Montréal, QC, Canada). My research interests include embedded system modeling, probabilistic software timing analysis and multi-processor system-on-chip design.

Current Projects

My doctoral research focuses on probabilistic timing analysis. For high-performance time-critical aerospace computer system, such as a satellite, the accurate timing prediction of software execution plays an important role. However, to address increasing complexity in computer applications, more advanced architectures using multi-stage pipelines, several memory hierarchy levels and even Multi-Processor System-on-Chip (MPSoC) designs are proposed for high performance computing. These traditional deterministic computer architectures make software timing behavior almost impossible to accurately predict. A conservative estimation will place the Worse Case Execution Time (WCET) far away from the actual maximum time used by the application. In this research project, I address the issue using probabilistic real-time system software. The idea is that the timing behavior of a system can be defined by probabilistic metrics applied to software. With probabilistic software methodology for timing prediction, the execution time will have a smoother distribution and avoid corner cases. This will reduce overestimation and time-critical system can benefit tremendous in terms of cost of integration, verification and certification.

Selected Publications

C. Chen, L. Santinelli, J. Hugues and G. Beltrame, “Static probabilistic timing analysis in presence of faults,” 2016 11th IEEE Symposium on Industrial Embedded Systems (SIES), Krakow, 2016, pp. 1-10.

C. Chen, J. Panerati and G. Beltrame, “Effects of online fault detection mechanisms on Probabilistic Timing Analysis,” 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Storrs, CT, 2016, pp. 41-46.

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