Bio and Research Interest
I received my M.Sc. degree in Electrical Engineering from M'Hamed Bouguara University (BM, Algeria) in 2014, and a B.Sc. in Electrical Engineering from the Institute of Electrical and Electronic Engineering -IGEE- (BM, Algeria) in 2011. I am currently a PhD student at Ecole Polytechnique de Montreal (QC, Canada) under the supervision of Giovanni Beltrame and a member of the MISTLab.
In past years, I competed in the LG Global Challenger 2011 as a team leader that ranked among the top five. I also led a team on the Startup Weekend Women edition'12 where we ranked among the top nine.
My research interests lay in Machine Learning, Bio-inspired Optimization Techniques, Pattern Recognition, Embedded Systems, Real-time Scheduling
Hardware-aware Real Time Code Generation
In software simulation development, subject matter experts (SMEs) are hardly expected to translate their expertise in different domains into an imperative programming language, thus leading to the use of DSLs to transfer their knowledge. In the process, performance is traded for usability to cope with software complexity; A matter that is becoming increasingly difficult without a considerable knowledge of the hardware and expertise in parallel programming.
Our goal in this project is to define a methodology to hide software complexity from SMEs and extract the maximum performance from the hardware by taking into account inputs from SMEs and hardware and software experts to automate the software generation, mapping and optimization.
This methodology will be applied in particular to the aerospace industry, and precisely to Full Mission Simulators (FMSs), which are applications that are developed and maintained by multiple SMEs.
I worked previously on an autonomous self-parking car based on SOPC. We built our system on an RC-toy car that detects a parking space, judges the adequacy of said space and then proceeds to park in either parking positions; parallel, or perpendicular. It could also leave a parking space after it was parked. The system was built on the DE2 Altera FPGA board and used the soft-core technology NIOS-II.
During my Masters degree, I received a teaching assistantship for two years to supervise and handle the lab work for Digital Systems Design with VHDL course at IGEE.